PCB, also known as a Printed Circuit Board, enables electrical connections between electronic components and facilitates functional implementation. It is a crucial component in power circuit design.
This article will introduce the fundamental rules for PCB layout and routing.
Basic Component Placement Rules
1. Layout components by circuit modules. Related circuits performing the same function constitute a module. Components within a module should be grouped as closely as possible, while digital and analog circuits should be separated.
2. Do not place components within 1.27mm of non-mounting holes such as positioning holes or standard holes. Keep a clearance of 3.5mm (for M2.5) or 4mm (for M3) around mounting holes like screw holes.
3. Avoid placing vias beneath horizontally mounted components such as resistors, inductors (through-hole), and electrolytic capacitors to prevent short circuits between the via and component housing after wave soldering.
4. Maintain a minimum distance of 5mm between the outer edge of any component and the board edge.
5. Ensure a minimum distance of 2mm between the outer edge of a surface-mount component pad and the outer edge of an adjacent through-hole component.
6. Metal-cased components and metal parts (e.g., shielding boxes) must not contact other components or be flush with printed traces/pads; maintain a minimum clearance of 2mm. Positioning holes, fastener mounting holes, oval holes, and other square holes on the board must be at least 3mm from the board edge;
7. Heat-generating components must not be adjacent to conductors or thermally sensitive components; high-heat devices should be evenly distributed;
8. Power sockets should be placed near the board edges whenever possible. Power sockets and their corresponding busbar terminals should be arranged on the same side.
Particular care must be taken to avoid placing power sockets or other soldered connectors between connectors to facilitate soldering, power cable routing, and cable management.
Spacing between power sockets and soldered connectors should allow for easy insertion and removal of power plugs;
9. Placement of other components: All ICs should be aligned on one side. Polarized components must have clearly marked polarity.
On a single PCB, polarity markings should not exceed two directions. When two directions are present, they must be perpendicular to each other;
10. PCB routing density should be appropriately balanced. Where density differences are significant, fill with a copper mesh pattern with a grid size greater than 8 mil (or 0.2 mm);
11. No through-holes shall be present on SMD pads to prevent solder paste loss causing component solder joint failure. Critical signal traces shall not cross between connector pins;
12. SMD components shall be aligned on one side only, with consistent character orientation and package direction;
13. Polarized components on the same board shall maintain consistent polarity marking directions.
Basic Component Routing Rules
1. No routing within 1mm of PCB edges or within 1mm of mounting holes;
2. Power traces should be as wide as possible, no less than 18mil; signal traces no less than 12mil; CPU I/O traces no less than 10mil (or 8mil); trace spacing no less than 10mil;
3. Standard vias no less than 30mil;
4. Dual In-Line Package (DIP): Pad 60mil, hole 40mil; 1/4W Resistor: 51*55mil (0805 SMD); DIP version: Pad 62mil, hole 42mil; Non-Polarized Capacitor: 51*55mil (0805 SMD); DIP version: Pad 50mil, hole 28mil;
5. Ensure power lines and ground lines are routed radially whenever possible, and avoid looping signal lines.
Enhancing Interference Resistance and Electromagnetic Compatibility
When developing electronic products with processors, how can interference resistance and electromagnetic compatibility be improved?
1. The following systems require special attention to electromagnetic interference resistance:
(1) Systems with microcontrollers operating at extremely high clock frequencies and exceptionally fast bus cycles.
(2) Systems containing high-power, high-current drive circuits, such as spark-generating relays or high-current switches.
(3) Systems with weak analog signal circuits and high-precision A/D conversion circuits.
Enhance Electromagnetic Interference Resistance
Implement the following measures to enhance electromagnetic interference resistance:
(1) Select microcontrollers with lower operating frequencies:
Selecting microcontrollers with lower external clock frequencies can effectively reduce noise and enhance system immunity.
Compared to sine waves, square waves of the same frequency contain significantly more high-frequency components.
Although the amplitude of these high-frequency components is smaller than the fundamental wave, higher frequencies are more prone to emission and become noise sources.
The high-frequency noise generated by microcontrollers that causes interference is approximately three times the clock frequency.
(2) Reducing signal distortion during transmission
Microcontrollers are primarily manufactured using high-speed CMOS technology.
The static input current at the signal input terminal is around 1mA, with an input capacitance of approximately 10pF, resulting in a very high input impedance.
The output terminals of high-speed CMOS circuits possess significant load-driving capability, meaning they can deliver substantial output values.
When the output of a gate is routed through a long cable to an input terminal with very high impedance, reflection issues become severe. This causes signal distortion and increases system noise.
When Tpd > Tr, the issue becomes one of transmission lines, necessitating consideration of signal reflection and impedance matching.
Signal delay time on a printed circuit board (PCB) correlates with the characteristic impedance of the trace, which in turn relates to the dielectric constant of the PCB material.
As a rough estimate, signal propagation speed through PCB traces ranges from one-third to one-half the speed of light. In microcontroller-based systems, the typical Tr (standard delay time) for logic components is between 3 and 18 ns.
On a printed circuit board, a signal traversing a 7Ω resistor and a 25cm-long lead experiences a delay of approximately 4 to 20ns.
Therefore, signal leads on printed circuits should be as short as possible, ideally not exceeding 25cm. Additionally, the number of vias should be minimized, preferably not exceeding two.
When a signal’s rise time exceeds its delay time, fast electronics principles apply. Impedance matching of transmission lines must be considered.
For signal transmission between integrated circuits on a single PCB, avoid situations where Td > Trd. Larger PCBs inherently limit system speed capabilities.
The following conclusion summarizes a fundamental PCB design rule: Signal delay time on the board must not exceed the nominal delay time of the components used.
(3) Reducing Cross-Interference Between Signal Lines:
At point A, a step signal with rise time Tr propagates along line AB toward point B. The delay time Td occurs along line AB.
At point D, due to the forward propagation of the signal from point A, the reflected signal from point B, and the delay Td along line AB, a positive pulse signal with width Tr is induced after Td elapses.
At point C, due to signal transmission and reflection on AB, a positive pulse signal with a width twice the delay time on AB (i.e., 2Td) is induced. This constitutes crosstalk interference between signals.
The intensity of the interference signal correlates with the di/at of the signal at point C and the inter-wire distance. When the two signal lines are not very long, what is observed on AB is essentially the superposition of two pulses.
Microcontrollers manufactured using CMOS technology feature high input impedance, high noise levels, and high noise tolerance.
Adding 100–200 mV of noise to digital circuits does not affect their operation. However, if line AB in the diagram carries an analog signal, this interference becomes intolerable.
Cross-interference between signals is reduced when using a four-layer printed circuit board with one layer as a large ground plane, or a double-sided board where the reverse side of the signal trace is a large ground plane.
This occurs because the large ground plane lowers the characteristic impedance of the signal trace, significantly reducing reflections at the D-end.
Characteristic impedance is inversely proportional to the square of the dielectric constant of the medium between the signal trace and ground, and directly proportional to the natural logarithm of the medium’s thickness.
If lines AB carry an analog signal, to prevent interference from digital signal lines CD, a large ground plane should be placed beneath lines AB.
The distance between lines AB and CD should be at least 2-3 times the distance between lines AB and the ground plane.
Localized ground shielding can be employed by routing ground traces on both sides of the connection points.
(4) Reducing Noise from Power Supplies
While supplying energy to the system, power supplies also inject noise into the circuits they power.
Microcontroller reset lines, interrupt lines, and other control lines in circuits are particularly susceptible to external noise interference.
Strong interference from the power grid enters circuits via power supplies. Even battery-powered systems are affected, as batteries themselves generate high-frequency noise.
Analog signals in analog circuits are especially vulnerable to interference from power sources.
(5) Consider the High-Frequency Characteristics of Printed Circuit Boards and Components
At high frequencies, the distributed inductance and capacitance of leads, vias, resistors, capacitors, and connectors on printed circuit boards cannot be ignored.
The distributed inductance of capacitors must not be overlooked, nor the distributed capacitance of inductors.
Resistors cause reflections of high-frequency signals, while the distributed capacitance of leads becomes significant.
When the lead length exceeds 1/20 of the noise frequency’s corresponding wavelength, an antenna effect occurs, radiating noise outward through the leads.
A via on a printed circuit board introduces approximately 0.6 pF of capacitance. The packaging material of an integrated circuit itself introduces 2 to 6 pF of capacitance.
A connector on a PCB has 520 nH of distributed inductance. A dual in-line package (DIP) socket for a 24-pin IC introduces 4–18 nH of distributed inductance.
These small distributed parameters are negligible in microcontroller systems operating at lower frequencies; however, they require special attention in high-speed systems.
(6) Rational Component Zoning
Component placement on printed circuit boards must fully consider electromagnetic interference mitigation. A fundamental principle is to minimize interconnect lengths between components.
Layout should logically separate three areas: analog signal sections, high-speed digital circuits, and noise sources (e.g., relays, high-current switches), minimizing signal coupling between them.
Proper grounding: Power lines and ground planes are critical on printed circuit boards. Grounding is the primary method for overcoming electromagnetic interference.
For double-sided boards, grounding layout is particularly critical. Using single-point grounding, power and ground are connected to the PCB from opposite ends of the power supply—one connection for power and one for ground.
Multiple return paths for ground must converge at the power connection point, achieving single-point grounding.
Separating analog ground, digital ground, and high-power device ground refers to routing them separately while converging at this grounding point.
When connecting to signals outside the PCB, shielded cables are typically used. For high-frequency and digital signals, both ends of the shielded cable should be grounded.
For low-frequency analog signals, grounding one end of the shielded cable is preferable.
Circuits highly sensitive to noise and interference, or those subject to severe high-frequency noise, should be shielded with a metal enclosure.
(7) Utilizing Decoupling Capacitors Effectively
High-quality high-frequency decoupling capacitors can eliminate components up to 1GHz. Ceramic chip capacitors or multilayer ceramic capacitors exhibit superior high-frequency characteristics.
When designing printed circuit boards, a decoupling capacitor should be placed between the power supply and ground pins of each integrated circuit.
Decoupling capacitors serve two purposes: first, they act as storage capacitors for the integrated circuit, providing and absorbing the charging/discharging energy during the circuit’s turn-on/turn-off transitions; second, they bypass high-frequency noise from the device.
A typical decoupling capacitor in digital circuits is 0.1μF. With a distributed inductance of 5nH, its parallel resonance frequency is approximately 7MHz. This means it effectively decouples noise below 10MHz but is nearly ineffective for noise above 40MHz.
Capacitors rated at 1μF or 10μF exhibit parallel resonance frequencies above 20MHz, offering superior high-frequency noise rejection.
Installing a 1μF or 10μF high-frequency decoupling capacitor near the power input point on the printed circuit board is beneficial, even in battery-powered systems.
For every 10 or so integrated circuits, add one charge/discharge capacitor (also called a storage capacitor), with a recommended value of 10μF.
Avoid electrolytic capacitors, as their rolled-film structure exhibits inductive behavior at high frequencies. Instead, use ceramic or polycarbonate capacitors.
Decoupling capacitor values are not strictly fixed; they can be calculated as C = 1/f. For example, 0.1μF is suitable for 10MHz. For systems built around microcontrollers, values between 0.1μF and 0.01μF are acceptable.
Practical Tips for Reducing Noise and Electromagnetic Interference
(1) Use low-speed chips where possible; reserve high-speed chips for critical applications.
(2) Reduce the rise/fall rates of control circuit edges by adding a series resistor.
(3) Provide some form of damping for components like relays.
(4) Use a frequency clock that meets system requirements.
(5) Position the clock generator as close as possible to devices using that clock. Ground the housing of the quartz crystal oscillator.
(6) Enclose the clock area with a ground plane, keeping clock traces as short as possible.
(7) Position I/O driver circuits near the PCB edge for rapid trace exit. Filter signals entering the PCB and those originating from high-noise areas. Implement series termination to minimize signal reflections.
(8) The unused terminal of the MCD must be connected to a high potential, grounded, or defined as an output terminal. All terminals on the integrated circuit that should be connected to the power supply ground must be connected; do not leave them floating.
(9) Do not leave unused gate circuit input terminals floating. For unused operational amplifiers, connect the positive input terminal to ground and the negative input terminal to the output terminal.
(10) Use 45-degree bends instead of 90-degree bends in PCB routing to minimize high-frequency signal radiation and coupling.
(11) Zone the PCB based on frequency and current switching characteristics. Place noise-generating components farther away from noise-sensitive components.
(12) For single- and double-sided boards, employ single-point power and ground connections. Use thick power and ground traces. Where economically feasible, use multilayer boards to minimize capacitive coupling between power and ground.
(13) Keep clock, bus, and chip select signals distant from I/O lines and connectors.
(14) Keep analog voltage input lines and reference voltage terminals as far as possible from digital signal lines, especially clocks.
(15) For A/D devices, prioritize integrating digital and analog sections rather than crossing them.
(16) Clock lines perpendicular to I/O lines cause less interference than parallel ones; position clock component pins away from I/O cables.
(17) Keep component leads as short as possible, including decoupling capacitor leads.
(18) Critical traces should be as wide as feasible and include protective ground planes on both sides. High-speed traces should be short and straight.
(19) Noise-sensitive traces should not run parallel to high-current or high-speed switching traces.
(20) Avoid routing traces beneath quartz crystals or noise-sensitive components.
(21) Prevent current loops around weak-signal circuits and low-frequency circuits.
(22) Avoid signal loops entirely; if unavoidable, minimize loop area.
(23) Provide one decoupling capacitor per integrated circuit. Add a small high-frequency bypass capacitor adjacent to each electrolytic capacitor.
(24) Use high-capacitance tantalum or polyimide capacitors instead of electrolytic capacitors for circuit charging/discharging energy storage. When using tubular capacitors, ground the casing.
